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MPC-106/PCI - MITAC MPC-106/PCI PCI Flat Panel Control Card Simple Type: System

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MITAC MPC-106/PCI PCI Flat Panel Control Card Simple Type: System

The MPC106 is one device in a family of products that provides system-level support for industry-standard interfaces to be used with PowerPC microprocessors. The MPC106 provides a common hardware reference platform (CHRP) compliant bridge between the PowerPC architecture defined microprocessor family and the peripheral component interconnect (PCI) bus. CHRP is a set of specifications that defines a unified system architecture. PCI support allows system designers to design systems rapidly, using peripherals already designed for PCI and the other standard interfaces available in the personal computer hardware environment. These open specifications make it easier for system vendors to design systems capable of running multiple operating systems. The MPC106 integrates secondary cache control and a high-performance memory controller. The MPC106 uses an advanced, 3.3-V CMOS process technology and is fully compatible with TTL devices.

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  • 32-bit address bus, 64-bit data bus
  • 60x processor interface
  • Compliant with PCI Local Bus Specification, Revision 2.1
  • Configurable for write-through or write-back operation
  • Decoupled address and data buses for pipelining of 60x accesses
  • Direct-mapped
  • Gbyte of RAM space, 16 Mbytes of ROM space
  • High-bandwidth, 64-bit data bus (72 bits including parity or ECC)
  • Programmable interface timing
  • SDRAM interface supports 64- and 128-Mbit, 4- and 2-bank SDRAMs with 2 open pages simultaneously and 16-Mbit, 2-bank SDRAMs with 2 open pages simultaneously
  • Secondary (L2) cache control
  • Selectable big- or little-endian operation
  • Store gathering on 60x-to-PCI writes
  • Supports 1 to 8 banks of DRAM/EDO/SDRAM with sizes ranging from 2 to 128 Mbytes per bank
  • Supports accesses to all PCI address spaces
  • Supports byte parity
  • Supports cache sizes of 256 Kbytes, 512 Kbytes, and 1 Mbyte
  • Supports fast page mode DRAMs, extended data out (EDO) DRAMs, or synchronous DRAMs (SDRAMs)
  • Supports full memory coherency
  • Supports optional 60x local bus slave
  • Supports partial update with external byte decode for write enables
  • Supports PCI interlocked accesses to memory using LOCK signal and protocol
  • Supports up to four 60x processors
  • Supports various operating frequencies and bus divider ratios
  • Up to 4 Gbytes of cacheable space




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